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Diplom-/Masterarbeit: Modeling and evaluation of a cache coherence mechanism for embedded multi-core architectures
15.02.2010, Diplomarbeiten, Bachelor- und Masterarbeiten
In the scope of this thesis, a cache coherence mechanism should be modeled, integrated and evaluated in our existing simulator for system-level design space exploration of Multiprocessor Systems-On-Chip (MPSoCs).
Kontakt: roman.plyaskin@tum.de
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http://www.lis.ei.tum.de/fileadmin/downloads/ausschreibungen/DM_coherence.pdf
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